Explore the critical challenges of nano-scale CMOS design in ‘DESIGN FOR MANUFACTURABILITY AND YIELD FOR NANO-SCALE CMOS’. As technology nodes shrink to 32 nm, issues like printability, planarization, and intra-die variability demand immediate attention. This essential guide integrates manufacturability and yield directly into the IC design process. It covers everything from standard cell design and library yield-grading to advanced techniques like CMP simulation, dummy-fill insertion, mask planning, and statistical timing closure. Learn best practices and avoid common pitfalls to enhance design manufacturability and yield. An indispensable resource for practicing IC designers and graduate students in IC design or EDA tool development, available at The Bookish Owl.